Nvidia Deploys Vera CPUs and AI Agents to Compress Chip Design From Weeks to Hours

Quick Facts

• Nvidia’s Vera CPU delivers more than 1.8x higher agentic sandbox performance than traditional x86 architectures and can run 22,500 concurrent agent environments from a single rack enclosure.
• Synopsys’s autonomous verification flow achieved up to 50x faster time-to-validated RTL with a 20% improvement in coverage; Cadence’s ChipStack agents cut a five-week verification loop to less than a day.
• Nvidia expanded its Agent Toolkit at DAC 2026 to include PhysicsNeMo and new CUDA-X libraries, letting AI agents call accelerated physics solvers as standard tools.

Nvidia used the 2026 Design Automation Conference in Long Beach, California, on July 26 to announce that its Vera CPU is now deployed across the electronic design automation workflows used to build its next generation of chips. The company also expanded its Nvidia Agent Toolkit for engineering to include PhysicsNeMo physics-AI libraries and a new set of CUDA-X math libraries.

The additions mean AI agents can call accelerated physics solvers the same way they call any third-party tool, pulling GPU-accelerated simulation directly into automated design loops.

The Vera CPU

Nvidia unveiled Vera at its GTC Taipei keynote on May 31, 2026. The chip uses 88 custom Olympus cores and an LPDDR5X memory subsystem delivering 1.2 TB/s of bandwidth. Nvidia built it around the specific demands of agentic workloads: Python runtimes, sandboxed code execution, orchestration logic, and memory-heavy tool calls.

The Olympus core delivers up to 50% higher instructions-per-clock than Nvidia’s Grace architecture. Compared to AMD’s Turin, Nvidia claims up to 1.9x IPC gains, 2.3x more branch predictions per cycle, and 2.4x higher instruction fetch operations per cycle.

Jensen Huang, Nvidia’s founder and CEO, described the rationale plainly: “AI agents will be the largest users of computing. Vera is the first CPU designed for that future.”

EDA Gains With Cadence and Synopsys

Nvidia is collaborating with Cadence and Synopsys to optimize their EDA applications for the Vera CPU. Cadence Jasper, a formal verification tool, and Synopsys VCS, used for functional verification, each showed up to 1.5x higher throughput on select workloads running on Vera.

The agent-driven gains go further. Synopsys’s fully autonomous verification closure flow compressed weeks of manual labor into hours, reaching up to 50x faster time-to-validated RTL and a 20% improvement in coverage. Cadence’s ChipStack AI Super Agent delivered over 40x faster RTL validation cycles, cutting a typical five-week verification loop to less than a day.

Paul Cunningham, senior vice president and general manager of the System Verification Group at Cadence, said the company is “moving from AI that assists engineers to autonomous virtual engineers that can implement real design and verification work.”

New Libraries Push Simulation Speed

Three new CUDA-X libraries debuted at DAC 2026. cuISS handles iterative solvers. cuDSS targets direct sparse solvers used in circuit and device simulation. cuEST addresses quantum-chemistry simulations that predict how materials behave at the atomic scale.

Nvidia also updated CUDA-X libraries to support iterative sparse solvers on its GPUs for the first time. The sparse linear algebra arithmetic involved underpins physical simulations across multiple domains.

The results from partners are sharp. Keysight Technologies accelerated electromagnetic simulations by up to 10x using the cuDSS libraries. Silvaco Group ran a 3.2 billion-mesh-node photonic edge coupler simulation in under four hours on a cluster of 32 GPUs. Synopsys PrimeSim SPICE posted roughly 18x faster wall-clock time by running on Nvidia GPUs versus CPU-only setups.

What This Means for Engineering Teams

Ian Buck, Nvidia’s vice president of hyperscale, said agentic workloads have made CPUs “much more integral” to the overall compute picture. A single Vera CPU rack can run 22,500 concurrent agent environments, which changes the math on how many parallel design experiments an engineering team can run at once.

The practical shift is this: verification work that required weeks of engineer time now runs autonomously in hours. Teams can test more design alternatives, catch bugs earlier, and move faster through tape-out cycles. For software companies building on custom silicon or evaluating AI infrastructure vendors, Nvidia’s direction signals that agentic automation is moving from experiment to standard workflow inside the world’s largest chip design operation.

Read more: Nvidia is putting its Vera CPUs to work alongside AI agents to speed up chip design