Quick Facts
- Architect Labs, a Palo Alto chip startup with $24 million in seed funding, says its AI system designed and fully verified an inference chip called Redwood in under two weeks from a human-written specification.
- The chip has run only on an AMD Versal FPGA at 250 MHz. Performance claims comparing it to NVIDIA’s Jetson Orin Nano are projections for a not-yet-built Samsung 8nm implementation.
- Architect Labs claims the AI system also demonstrated recursive self-improvement, using a model deployed on the chip to suggest optimizations for the next generation of the design.
A startup called Architect Labs says its AI system did what a full team of semiconductor engineers once required months to accomplish. Two human architects wrote a high-level specification. The system handled everything else.
The company announced on August 27, 2026 that its platform generated 100% of the RTL, verification environments, formal verification, firmware, drivers, and custom compute kernels for an AI accelerator called Redwood. The full process took fewer than 14 days. No human verification engineers participated.
What the System Built
Redwood uses a tile-based, near-memory dataflow architecture. The design keeps compute close to memory to cut energy costs from moving data. On an AMD Versal FPGA running at 250 MHz, Redwood Nano achieved 12.1 tokens per second on the Qwen3 0.6B model. NVIDIA’s Jetson Orin Nano, running at 1020 MHz, achieved 28 tokens per second on the same model.
Architect Labs projects that a Samsung 8nm version of Redwood would deliver 1.75x the throughput at 1.9x lower power than the Jetson Orin Nano. That would amount to a 3.4x improvement in performance per watt. The company also projects an order-of-magnitude gain in area efficiency over the Jetson.
Verification results were notable on their own. Every block hit 95% code and functional coverage. No bugs appeared in the first RTL design sent from simulation to the FPGA. Optimization runs that previously took 15 hours dropped to 15 to 30 minutes on the FPGA. When specification changes were made, a revised design was back on hardware in under 48 hours.
The Recursive Self-Improvement Claim
Architect Labs made a second claim that drew attention from the research community. The team deployed Qwen3 on Redwood, exposed it as an inference endpoint inside its own AI platform, and sampled the model repeatedly. The model identified timing improvements and kernel optimizations for several of its own operations.
The company’s research team wrote: “We believe this is one of the earliest demonstrations of recursive self-improvement: an AI system designed an AI accelerator, deployed an AI model on it, and used that model to improve a future generation of the accelerator.” At peak velocity, the design absorbed 115 merged changes in a single day.
What Remains Unproven
Chip-industry veterans pushed back on how the results were framed. Redwood does not yet exist in silicon. The NVIDIA performance comparison is a simulation-based projection calibrated against FPGA results, not a measured benchmark from a fabricated part. The phrase “beats NVIDIA” would carry weight after tape-out. Before it, the claim is forward-looking.
The backlash was partially fair. Architect Labs did not build a chip. It built a design that ran on a commercial FPGA board. The company knows this. Its next step is fabrication.
Company and Funding
Architect Labs emerged from stealth in June 2026 with $24 million in seed funding led by Kindred Ventures. Participants included TQ Ventures, Race Capital, and Together Fund, along with individual investors from NVIDIA, Google, OpenAI, and Anthropic. The company has 18 employees with backgrounds spanning semiconductor engineering and machine learning research.
Co-founder Ebrahim Hussain framed the problem plainly: “AI models have advanced dramatically across nearly every field, yet chip development cycles remain equally slow and painful.” The company’s stated goal is to let chip companies reach the market faster and let workload owners design their own ASICs without building a traditional engineering organization around it.
The Redwood demonstration is a proof of methodology, not a shipping product. If the design survives fabrication and the projected numbers hold in silicon, the implications for custom chip development at software companies would be significant. That test is still ahead.
Read more: An AI system designed an inference chip in two weeks. Now Architect Labs has to prove it in silicon